Qudos Work Experience

Qudos was based in Cambridge Science Park, Cambridge, UK, and produced ASIC chip designs. An ASIC chip has an array of transistors laid out, but is missing the top-level aluminium interconnect to wire the transistors together. An ASIC chip design consists of a wiring diagram that connects the transistors so as to perform a desired function. This wiring diagram is then sent to a fabricator for production of the actual chip.

Qudos had some extremely sophisticated CAD software written in Modula-2 to design the chips. It would take as input a desired circuit schematic, and an initial chip layout. It would permit the user to graphically place a gate from the circuit onto the chip layout. It could then attempt to layout specific wires, avoiding existing wires. The user could graphically correct the wires, or create new wiring. Finally, the product would verify the layout for correctness against the input circuit, and also perform simulations.

To do this work, the program had to be given the correspondence between a circuit element and a portion of the transistors laid out on the chip. Often, there were whole families of related circuit elements, such as NAND gates with 2, 3, 4, 6, and 8 inputs. Specifying all these circuit elements was very tedious.

Hence, during my work there from July to September 1989, I extended the CAD program to accept parameterized descriptions of circuit elements, such as a NAND gate with x inputs, where x can vary between 2 and 8. This greatly reduced the grunt-work involved in specifying the layout of a new chip.

Doing this was supposed to last all summer, but I finished it in about half the time. So I spent a month or so actually inputting the data for a new chip, working from a large-scale paper diagram, breaking it up into rectangles, and creating them as areas using the CAD package.

Rujith de Silva
Created 2001-03-01; modified 2001-03-01